The use of buried contact in integrated circuit is principally for the connection between polysilicon and the N.sup.+ region of silicon substrate. The buried contact is particularly popular for the CMOS SRAM manufacturing process. The conventional process involving the fabrication of buried contact is shown in FIGS. 1.about.4 and the relevant descriptions are as follows.
The steps for forming buried contact are shown in FIGS. 1.about.4 and inclusive of:
1) forming an oxide layer 2 on a p-type silicon substrate 1; PA1 2) depositing a first polysilicon layer 3 on the oxide layer 2 for protecting the oxide layer 2 which serves as a gate dielectric layer from environmental contamination; PA1 3) applying a photoresist mask 4 onto the first polysilicon layer 3, and defining a buried contact region by way of photolithography; and PA1 4) etching a portion of the first polysilicon layer 3 and the gate oxide layer 2 according to the shape of the photoresist mask 4 to form buried contact.
After the buried contact is obtained, the photoresist mask 4 is removed, and a second polysilicon layer 6 is deposited on the buried contact 5 and the unetched portion of the first polysilicon layer 3, as shown in FIG. 3. The resistance of the first and the second polysilicon layers 3 and 6 can be reduced by a diffusion process which is executed in a high temperature furnace and utilizes POCl.sub.3 as gas source. Meanwhile, an N.sup.+ region 7 is formed in the silicon substrate under the buried contact 5. Referring to FIG. 4, another photoresist mask 14 is formed on the surface of the second polysiIicon layer 6, and the desired source/drain region can be defined by photolithography technique. Then, the source/drain region can be obtained by plasma etching the second and the first polysilicon layers 6 and 3.
Because the etching selectivity of the polysilicon over the silicon substrate is about 1:1, the silicon substrate 1 will be etched at the same rate as that of the etching process for etching polysilicon layers 6 and 3, and thus a trench 8 will possibly be formed. The existence of the trench 8 may provide a current-leakage path between the N.sup.+ region 7 and the silicon substrate 1 so that the property of the device is adversely affected.